In order to ensure correct functioning of an integrated semiconductor memory, for example, a DRAM (Dynamic Random Access Memory) semiconductor memory, it is essential to monitor internal time sequences within the integrated semiconductor memory. The time durations to be monitored may be, for example, delay times generated by circuit components of the integrated semiconductor memory during individual successive operating operations of the semiconductor memory. Furthermore, a specific time duration is required to elapse during operating operations such as, for example, read accesses to a memory cell or the turn-on of selection transistors of a memory cell.
If a logic information item is intended to be stored in a DRAM memory cell, then the selection transistor of the memory cell has to be turned on for a certain time until electrodes of a storage capacitor have been charged to a specific voltage. When reading from a memory cell, the charge state on the storage capacitor alters the potential of a connected bit line. However, the change in potential on the bit line becomes apparent only after a certain delay time has elapsed, so that a connected sense amplifier can be activated, for example, only after this time has elapsed.
Many of the internal chip times of interest can currently only be measured at the wafer level. This is due to the fact that the measurement locations on the integrated semiconductor chip are only accessible when the housing is open. Furthermore, complex test systems are required for measuring the time sequences that are becoming ever shorter. Such test systems are generally very expensive and continually have to be replaced by newer, faster test systems in the course of the rapid development in the semiconductor memory market.